The present disclosure relates to digital circuit simulation, and more particularly relates to distributed simultaneous simulations.
Generally, post-layout simulation has no relation to pre-layout simulation. The post-layout simulation needs to be executed for each circuit layout, and requires significant simulation time.
The simulation time of a conventional simulation system increases exponentially with an increasing circuit size. If there is an error during a functional verification, an additional simulation needs to be made from the beginning up to the error time, after detecting the error position by searching backwards from the primary port in the top level.